As the integrated circuit industry becomes more and more competitive, there is a need for more efficient integrated circuits which deliver electronic messages at faster rates than is presently accomplished. To design faster parts, the capacitance associated with interconnects, passive and active devices need to be reduced. For PROMs which use a thin dielectric as the fusing element, the capacitance of the cell will be greatly affected by the capacitance of the thin dielectric. Generally, capacitance per unit area of a thin film capacitor is equal to the ratio of the area divided by the thickness of the dielectric.
In the past, this limitation of capacitance has been dealt with by reducing the area of the fuse region and increasing the thickness of the dielectric. Unfortunately thicker dielectrics require higher voltages for fusing (dielectric breakdown). This in turn makes the incorporation of high voltage devices to standard logic process flow more difficult. Higher voltage requirements will as well increase the device isolation space making the cell bigger.
For a given lithographic capability, the area of the fuse cell would be limited by the minimum size of the geometry than can be defined by lithography.
Therefore, there is a need for a thin dielectric system for lower programming voltage while at the same time having very small area to reduce the capacitance associated with the fuse dielectric.